1. Field of the Invention
The present invention relates to hardware design languages. More particularly, the present invention relates to an improved method for translating between Verilog and VHDL hardware design languages.
2. The Background
One well-known method for designing an ASIC or an FPGA-based digital circuit includes using an HDL (Hardware Description language). An HDL is a notation for describing an electronic circuit at a specified level of abstraction. Three types of abstraction levels are defined for an HDL: RTL (register-transfer level), gate-level, and transistor level. RTL abstraction describes the functional or behavioral characteristics of a circuit. Gate level abstraction describes a circuit using gate logic elements, such as OR, NOR, AND, NAND, and the like, and their interconnections, which form a netlist reflecting the circuit design when coupled together. The transistor level, sometimes referred to as a switch level, describes the circuit design usage transistors and their interconnections as the basic elements defining the properties of the circuit.
Specifying the level of abstraction enables a designer to model a circuit design at an abstraction level suitable for a particular design step. For example, if a top-down design process is used to implement a design specification, the designer may define a circuit design starting at a behavioral or functional level. This enables the designer to isolate the functional aspects of the proposed circuit design from testing and implementation (gate-level and/or target technology) issues that otherwise would have been complicating factors.
To minimize confusion in the following discussion, an HDL-based circuit design modeled at one of the above levels of abstraction will be referred to according to the level of abstraction used. For example, an HDL-based circuit design at the register-transfer level will simply be referred to as an RTL-based circuit design. Similarly, a structural circuit design at the gate level or at the transistor level will be referred to as a gate level-based circuit design or a transistor level-based circuit design, respectively.
Two types of hardware description languages are currently in wide use in the digital circuit design or EDA (Electronic Design Automation) industry: VHDL and Verilog HDL (hereinafter referred to as Verilog). VHDL is an abbreviation for VHSIC (very high-speed integrated circuit) Hardware Description Language. Both hardware description languages, however, are not compatible or interchangeable with respect to their respective tools, such as verification and simulation tools. This incompatibility, among other things, has promoted a divergence among design companies and companies that provide re-useable IP (Intellectual Property) core design modules into VHDL, and Verilog xe2x80x9ccamps.xe2x80x9d
For example, a design company that is experienced in Verilog will typically look to Verilog-based re-useable modules as a source for design components, while a design company experienced in VHDL will typically look to VHDL-based re-useable modules. For a design company to switch to an HDL other than the one it is experienced with or to mix and match between the two types of HDLs would be too costly and/or inefficient. Re-useable Soft Intellectual Property (IP) Core vendors are also affected by the incompatibility between the HDLs because if they do not offer modules based on both types of HDLs, they risk losing market share to competitors that do.
One conventional solution to the above problems includes creating in a top-down manner an HDL-based circuit design at the register-transfer level (the xe2x80x9cinitial RTL-based circuit designxe2x80x9d) and then translating the initial RTL-based circuit design to a target RTL-based circuit design. This approach includes at least three steps.
First, as shown in FIG. 1, a test bench 10 is created for the initial RTL-based design 12 so that a set of reference output vectors 18 may be obtained. Test bench 10 includes: a top-level module 14 representing a set of modules which comprise initial RTL-based design 12, and a set of input test vectors 16. Top-level module 14 is simulated using input test vectors 16, generating a set of reference output vectors 18, sometimes referred to as golden output vectors.
Second, as shown in FIG. 2, initial RTL-based circuit design 12 is translated into a target RTL-based circuit design 20 having a top-level module 38 using a code translation tool 21. For example, if initial RTL-based circuit design 12 is described using VHDL, then the target RTL-based circuit design 20 is described using Verilog, or vice versa. The translation from one HDL type to another HDL type is performed on a module by module basis at the register-transfer level by a code translator. For example, the module tar1.mod 22 is created by translating the module org1.mod 24 from its initial RTL-based circuit design to the target RTL-based circuit design. Similarly, modules tar2.mod 26, tar3.mod 28, and tar4.mod 30 are created by translating the modules org2.mod 32, org3.mod 34, and org4.mod 36, respectively, from their initial RTL-based circuit design to target RTL-based circuit design. After translation, target RTL-based circuit design 20 is typically checked for any coding violations.
Finally, as shown in FIG. 3, the translated files tar1.mod 22, tar2.mod 26, tar3.mod 28, and tar4.mod 30 are integrated into a top-level module 38 after all of the initial modules have been translated. A top-level module includes a set of modules (typically all of the modules) which form a particular circuit design and describe the logical flow or arrangement of the modules with respect to each other. Hence, a top-level module is a fully hierarchical description of a set of modules that form a particular circuit design.
After integration, top-level module 38 is simulated by running a test bench 40 using test input vectors 16, creating a set of test output vectors 42. Test output vectors 42 are then compared with reference output vectors 18 to determine the accuracy of the translation.
The above approach suffers from the following disadvantages. First, all of the initial modules must be translated before the target modules can be integrated and tested. This prolongs the translation process because the integration of the target modules into a top-level module for simulation and testing cannot begin until the last initial module has been translated. For example, if org1.mod, org2.mod, org3.mod, and org4.mod require 1 day, 3 days, 5 days, and 15 days, respectively, to translate into their corresponding target modules, then integration and testing cannot begin until the end of the 15th day.
Moreover, testing is performed on the RTL-based top-level module, i.e., all of the target modules are tested at once. This renders debugging difficult (and hence increases verification time) because any problems encountered cannot be easily limited to one target module. This scenario is more complex especially when the logic path traverses multiple levels of hierarchy.
Accordingly, a need exists for an improved method for translating an initial RTL-based circuit design to a target RTL-based circuit design, which has a reduced translation and integration period.
Further, a need exists for an improved method for translating from an initial RTL-based circuit design to a target RTL-based circuit design, which ensures exact functional equivalence between the initial RTL-based and target RTL-based circuit designs.
In a first aspect of the present invention, an HDL-based ASIC design is translated from a first RTL description to a second RTL description. The first RTL description describes the HDL-based ASIC design through a first set of modules arranged in a hierarchical manner. Translation includes: creating a reference gate-level netlist by synthesizing the HDL-based ASIC design described using the first RTL description; creating a second set of modules by translating the first RTL description of the first set of modules to the second RTL description module by module; and creating a combined RTL and gate-level design by integrating at least one module from the second set of modules within the reference gate-level netlist.
In a second aspect of the present invention, each module translated into the second RTL description is checked for compilation warning or error messages. If any warning or error messages are generated, each offending module is modified to eliminate the warning or error messages. In addition, each module that is described using the first RTL description may be functionally compared with each module that is described using second RTL description. If any functional discrepancy exits between corresponding first and second RTL modules, the offending module that is described using the second RTL description is modified to rectify the functional discrepancy.
In a third aspect of the present invention, a top-level simulation may also be performed on all of the modules that are described using the second RTL description.